As the complexities of modern digital ASICs and SoCs continue to grow, so too do the challenges of design verification and validation. For each design engineer, the typical semiconductor design team has 3 to 5 times as many verification engineers. These verification teams are tasked with ensuring that the design is correct and functional and that it will meet various performance requirements.
Several challenges add to the complexity of design verification, including the rising complexity of designs, the transition to more complex manufacturing processes, increasing innovation in process technology, and the impact of design features meant to improve security. Additionally, the process of validating and verifying the functionality is challenging as it involves multiple disciplines and tools.
Verification challenges have also grown exponentially as the number of sub components and IP have increased dramatically. Additionally, the use of complex design flows and the increase in complexity of physical processes have increased the complexity of designs. For example, the design of a System on Chip (SoC) consists of several large and often hard to verify blocks. These blocks are typically memory controllers, communication interfaces, and processor cores. Additionally, these functional blocks are integrated with one or more hard-wired input/output connections.
In addition to the design components themselves, modern designs also tend to integrate other complex features that require additional verification. For example, modern processors have multiple cores. While the cores themselves are relatively highly optimized, they are complex and require verification of the inter-core communication. Additionally, modern processors often employ multiple levels of cache. While verifying the individual blocks itself is challenging, verifying the interactions between the blocks under various operating modes is exponentially more so.
With the increased complexity of components and integration of new features, designers have widely adopted verification methodologies that allow them to verify their designs in blocks. This allows them to verify a block before integrating it with other blocks, as well as to verify its integration with other blocks after testing. For example, a block-level regression can be used to verify that a newly integrated block behaves as expected after being integrated with other blocks.
While verification has challenges, it is a critical part of the design process, and ensures that the design will function as intended when manufactured. In our next blog, we will dive deeper into some of the coordination and visibility issues faced by verification teams, and how they could be solved.
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