Enabling Better Designs Through Linting and Formal Verification Metrics

As designs get more complex and competitive pressures in the semiconductor space grow, the role of RTL Linters and Formal Verification is becoming more critical. As designs move into later stages, the value and ROI goes up as more and more critical bugs are found and eliminated. However, these tools generate a huge number of reports and metrics that need to be parsed, centrally stored, and analyzed for design teams to know which designs are high risk.

To address this, robust report parsing, metric aggregation, and reporting infrastructure is required for design teams to best utilize the results from their Linting and Formal Verification tools. The focus should be on the capabilities needed to support the data needs of design teams to identify critical bugs and high risk designs, since they end up becoming the bottleneck to advancing to the next stage.

To implement and use a centralized data infrastructure for lint reports, semiconductor design and CAD teams need answer these following questions:

  • Who is responsible for creating the parsers, cron jobs, and other infrastructure? How will it be maintained?
  • Who is responsible for reporting and analysis? How will it be maintained?
  • What reports and metrics are necessary for design teams to know which designs are high risk?
  • What is the data architecture? What are the data transformation and visualization requirements?

The benefits of such infrastructure, once deployed and maintained, are numerous:

  • Design teams will be able to better utilize their Linting and Formal Verification tools. They will be able to identify bugs and high risk designs and accelerate their design to market time.
  • Design teams will be able to better utilize their Formal Verification tools, since they will be able to catch more bugs and create better coverage of their designs.
  • The semiconductor companies will be able to track and report on their effort to improve the quality of their designs and introduce more blocks into FV.
  • The semiconductor companies will be able to better allocate their resources to speed up the FV effort, and to identify the highest risk designs and bugs.
  • Finally when new or unexpected errors show up, there is history to easily identify for example, when the last clean runs happened and the associated metadata

To learn more about how our solution can help you , contact us at: info@logarithmlabs.com.