The design of chips is an extremely complex process. It is challenging for design teams to gain end-to-end visibility into the ground truth of their design. This makes it hard to make data-driven decisions, to know where to focus the team’s efforts, and to be as productive as possible. A big part of this is to make sure all the key stakeholders and decision makers have the required level of visibility into the ground truth of the design, with the appropriate tooling in place and with as little effort as possible.
Currently, chip designers track various design metrics and roll them up to help key decision makers such as team leads, managers, engineering directors, and VPs understand the current status, rate of progress, and key blockers around the designs. These metrics are usually aggregated at a subteam, block, or flow stage level only, so it is difficult for decision makers to get a complete or holistic view of a design. The lack of visibility into holistic design metrics makes it hard to effectively coordinate across the design team, leading to potentially uncaught design failures, delays, and increased cost.
In order to coordinate across the design team, these metrics need to be continuously collected, aggregated, and made available when needed. However, these metrics are usually quite complex and are spread across multiple logs, reports, and repositories, making it hard to aggregate and analyze them automatically.
To make matters worse, the complexity of the design metrics is increasing exponentially as the industry marches down towards 7nm and beyond. For example, at 7nm, the number of process corners to be evaluated can be well over 100, and without automation, manual aggregation and analysis of these metrics for each process corner is untenable.
To cope with this growing complexity of chip design, design teams need to be able to automate status tracking and analysis. They need a way to automatically parse logs and reports to collect the appropriate metrics, process and analyze them, and generate reports to help managers understand the “ground truth” of their design and the impact of a design change.
Enabling this in an effective manner greatly reduces the amount of design iterations and reworks, and ensures that only high quality chips are released to manufacturing.
In our next blog, we will discuss one potential way to achieve this goal using The Logarithm Labs Engineering Automation Platform.
To learn more about how our solution can help you achieve this, contact us at: firstname.lastname@example.org.